You have to show that you’re still alive.”īy Hollywood standards, Blair was a late bloomer. “I always say how visibility matters for the disabled,” she says. In my bedroom, on the floor that I’m used to, I can dance.” “I understand why people with MS spend a lot of time in their homes,” Blair writes in her memoir. “I’m not really a public-pleasure person.” But at 50, and in the wake of a life-changing diagnosis, Blair has turned outward, becoming a proactive figure advocating for inclusion and accessibility in an industry that rarely prioritizes these things. “I’m definitely more of an independent actress, or the strange oddball,” she says. While she still grapples with certain MS complications, Blair says she has “stopped losing abilities.” In September, she competed on DWTS for five weeks, joining a growing number of people with known disabilities to appear on the show.īlair has always fancied herself a supporting player in Hollywood. The 2021 documentary Introducing, Selma Blair chronicled her life in the months following her diagnosis, as she prepared for a risky yet potentially life-altering stem cell transplant in the summer of 2019-a process Blair refers to as “rebooting the computer.” She is now in remission, meaning the disease is not progressing. It’s quite late here already and time to go to bed now.Since her diagnosis, Blair has opened up about her health so frequently and freely that she’s rapidly become one of the most prominent faces of disability advocacy in Hollywood. Just some remarks I noticed while toying around with your design. If you really want to keep +3V3VADC on internal layers for some reason, then route it around those signal lines. I assume the 4C16M16SA is some memory chip with lots of relatively high sped traffick? You really do not want to cut the GND plane below all those signal wires. This track cuts both trough the GND plane and through PWR.CU. I’m a bit surprised by the routing of +3.3VADC. For the decoupling capacitor it does help to bet better performance. The connection between the pad and the IC itself is already much longer then the via. I’m not sure if this is important though. I’ve also gotten into a habit myself of giving each GND pin 2 via’s, one on each side of the pad. Reason is you get the GND closer to all footprints, which reduces EMI. I would swap the PWR.Cu and GND.Cu layer. (Maybe someone with more knowledge can chime in too) There are a few things I would change though. Your PCB looks quite good, but I have not looked too deep into it (I’m also not an expert on this). I’ve moved some via’s around a bit, and all unconnected items disappeared, so they were because of via’s too close together and the clearance of one via overlapped with a via that should not have clearance.
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